This invention relates generally to frequency synthesizers and more particularly to a fractional-division frequency synthesizer which may be employed in radiotelephone communications equipment to generate one of a plurality of signals for use by the radio frequency transceiver.
Phase-locked loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a voltage controlled oscillator (VCO). In a single loop PLL, an output signal from the VCO is generally coupled to a programmable frequency divider which divides the frequency of the output signal by a selected integer number to provide a frequency divided signal to a phase detector which compares the phase of the frequency-divided signal to the phase of a reference signal from a fixed frequency oscillator which, often, is selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO in a manner which causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized.
When the integer number of the divisor is changed, the VCO output signal changes frequency by a discrete increment and, therefore, can be stepped from one output signal frequency to another depending upon the integer number value. Since the programmable divider divides by integers only, the output frequency step size is constrained to be equal to the reference signal frequency. The signal output from the phase detector generally contains signal pulses which could produce a substantial amount of noise and spurious signals in addition to the desired VCO output signal. The loop filter integrates the signal output from the phase detector to remove much of the noise and spurious signals but the loop filter integration time slows the process of locking to (or causing the PLL to arrive at) a desired VCO output signal frequency. Thus, with the single loop PLL, an engineering compromise must be struck between the competing requirements of loop lock time, output frequency step size, noise performance, and spurious signal generation.
In order to overcome the limitations of the single loop PLL, programmable frequency dividers capable of dividing by non-integers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. A discussion of fractional-division synthesis may be found in U.S. Pat. No. 4,816,774. As described therein, two accumulators are employed to simulate the performance of fractional synthesis of the switching between different integer values of divisors without the attendant spurious signals generated by such switching. The two accumulator technique acts to reduce the unwanted spurious signals both by cancellation and loop filter rejection.
The reference signal frequency for the fractional-division frequency synthesizer is, therefore, determined by the step size of the VCO output frequency multiplied by the non-integer value of the programmable divider divisor. The designer of radiotelephone communication equipment is always faced with the requirement to reduce size, complexity, and cost of the radiotelephone equipment. If the radiotelephone equipment employs digital transmission techniques, the digital equipment conventionally employs a reference signal oscillator to generate the clock for the digital equipment. This clock oscillator may become a source of additional spurious signal output in the VCO output signal and is an added element of cost and complexity.